module xmj_COUNTER_74163(
	input wire CLK, CLR_L, LOAD_L, ENP, ENT,
	input wire[3:0] D,
	output reg[3:0] Q,
	output wire RCO
);
	
	wire _add;
	assign _add = (CLR_L && LOAD_L && ENP && ENT);
	assign RCO = (Q == 4'b1111 && _add);
	
	always @(posedge CLK or negedge CLR_L) begin
		if(~CLR_L) Q <= 4'd0000;
		else if(~LOAD_L) Q <= D;
		else if(_add) Q <= Q + 1;
		else Q <= Q;
	end
	
endmodule
